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2025
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08
Reconfigurable multifunctional integrated optical computing chip
Author:
The development of artificial intelligence is driving the evolution of computing architecture towards higher performance, lower power consumption, and stronger adaptability. In recent years, photonic computing has been regarded as an important direction to break through the bottleneck of artificial intelligence computing due to its high speed, parallelism, and low power consumption. However, current integrated photonic chips generally face issues such as structural rigidity, single functionality, and weak model switching capabilities, making it difficult to meet the diverse operational needs of neural networks.
Recently, Professor Hu Xiaoyong, Researcher Yang Qifan, and Professor Gong Qihuang's team from the School of Physics at Peking University proposed a reconfigurable multifunctional integrated photonic computing chip. This chip is based on an innovative algorithm-hardware co-design architecture, combining a core computing unit of micro-ring resonators with cross-waveguide coupling and an optical frequency comb light source, supporting in-situ switching deployment of three mainstream neural network models: fully connected, convolutional, and gated recurrent networks, under a unified configuration. It achieves comprehensive coverage of multimodal tasks from images, text to speech, demonstrating strong computational flexibility and task adaptability. This solution provides a promising approach for efficient multi-task processing of chip-level photonic information. The related research results were published under the title “ Reconfigurable Versatile Integrated Photonic Computing Chip ” in eLight (selected for two phases of the Excellence Program).
Photonic chips, with their advantages of low power consumption, high speed, and large bandwidth, have opened new paths for artificial intelligence computing. Existing studies have implemented different neural network functions based on various photonic architectures, such as matrix multiplication operations based on Mach-Zehnder interferometers and dense connection layers based on diffraction units. However, these architectures generally adopt a single module corresponding to a single model design scheme, mainly suitable for static tasks based on feedforward neural networks, making it difficult to meet the complex task requirements for dynamic information processing and multi-model deployment. In recent years, hybrid photonic architectures have attempted to enhance system functionality through multi-module combinations, but they impose higher requirements on micro-nano manufacturing processes, restricting the practical application process. Therefore, developing a multifunctional photonic computing chip that achieves multi-model in-situ switching deployment based on a unified architecture, while supporting both static and dynamic tasks, remains a core challenge that urgently needs to be overcome in the current integrated photonic computing field.
This paper proposes a novel reconfigurable multifunctional integrated photonic computing architecture ( Figure 1a ): using a reconfigurable micro-ring resonator (MRR) array and a Mach-Zehnder interferometer (MZI) array as computing modules, combined with an optical frequency comb as the light source, to cover the computational needs at various stages of large-scale tasks, including feature extraction, temporal reasoning, and output decision-making. The core computing unit is based on cross-waveguide coupling micro-ring resonators, which achieve efficient parallel computing by controlling the information encoding methods at the two input ports of the cross-waveguide, combined with the wavelength multiplexing mechanism of the optical frequency comb and the resonant correspondence between different free spectral ranges (FSR) of the micro-rings. This scheme supports in-situ switching between fully connected neural networks, convolutional neural networks, and gated recurrent neural networks, accommodating multimodal information processing that includes static and dynamic images, text, and speech ( Figure 1b ), demonstrating the chip's strong computational flexibility and task adaptability.
To verify the feasibility of the proposed architecture, the research team used a silicon nitride platform microcavity integrated with a DFB laser to generate a single soliton optical frequency comb as the light source ( Figure 2a ),其FSR为100 GHz( Figure 2b ). The computing chip was fabricated and packaged based on the SOI platform ( Figure 2c ), integrating 208 reconfigurable photonic devices within a chip area of 3 mm × 8 mm. Test results show that the MZI ( Figure 2d ) and MRR ( Figure 2e ) computing units within the chip can achieve high-precision weight modulation, and the MRR's electrical tuning bandwidth exceeds 5 FSR_mrr ( Figure 2f ), providing reliable assurance for high parallel computing across multiple FSR_mrr channels. At a typical modulation rate of 10 GHz, the chip's adjustable units achieved a computational area efficiency of up to 2.45 TOPS/mm².
To comprehensively verify the universality and complexity processing capability of the proposed architecture in multimodal tasks, the research team demonstrated three representative applications on the designed chip: image recognition ( Figure 3a ), sentiment analysis ( Figure 3c ) and speech recognition tasks ( Figure 3f ). Among them, the image recognition task aims to evaluate the training efficiency and learning ability of the designed photonic neural network in typical computer vision scenarios. The research team conducted experiments on the MNIST and CIFAR-10 datasets ( Figure 3b ) and achieved test accuracies of 92.9% and 56.6%, respectively, demonstrating superior generalization performance and training efficiency even with only 81,920 trainable parameters, fully reflecting the advanced nature of the model architecture and the potential of the designed chip in optical computing. In the sentiment analysis task, the team focused on the network's ability to process temporal information. The sentiment classification model built on the IMDB dataset achieved a training accuracy of 99.2% and a test accuracy of 80.8% ( Figure 3d, e ), further validating the robustness and adaptability of this reconfigurable photonic architecture in handling dynamic text data. In the speech recognition task, the research team constructed a hybrid neural structure integrating fully connected, convolutional, and gated recurrent networks, demonstrating the complete end-to-end inference process from speech waveform to text ( Figure 3g, h The photon neural network has been validated for its broad application prospects in highly complex computational tasks. Systematic experiments across three types of tasks not only cover the core computational paths of mainstream artificial intelligence applications from static images to dynamic language and then to speech large model inference, but also substantively demonstrate the overall advantages of the proposed photonic computing chip in multi-model in-situ switching, providing a new paradigm for promoting the widespread deployment of integrated photonic technology in the next generation of artificial intelligence systems.
This study proposes a reconfigurable multifunctional integrated photonic computing chip that supports in-situ deployment of three mainstream neural network models: fully connected, convolutional, and gated recurrent networks, under a unified configuration, achieving comprehensive coverage of multimodal tasks from image recognition, sentiment analysis to speech recognition. By introducing a cross-coupled waveguide structure and optical frequency comb source, the chip achieves high parallel optical computing under the control of different wavelengths and free spectral ranges within a single structure, demonstrating strong model flexibility and task adaptability. This achievement provides a new paradigm for achieving multi-model in-situ switching while accommodating both static and dynamic tasks, which is of significant importance in advancing the process of integrated photonic chip artificial intelligence computing.
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